The present invention relates to a method of preparing high-k gate dielectrics by liquid phase anodic oxidation, and more particularly to a method of using liquid phase anodic oxidation to produce a gate dielectric layer of high quality, high-k (k being the dielectric constant) and ultrathin equivalent oxide thickness (EOT), which can be integrated with a complementary metal oxide semiconductor(CMOS) process directly.
The present technology of complementary metal oxide semiconductor processes has reached to the times of deep sub-micron devices. The more advanced nanotechnology processes(<100 nm) also have been researched and developed to a point where it is rapidly becoming close to where manufacturing will be implemented. Following the continuous advancements in process techniques of this technology, the gate-oxidizing layer of the transistor is getting thinner. Though the advantages of prior silicon dioxide can't be replaced, the leakage current in the accumulation region follows a trend of exponential growth with the reduction of thickness. Therefore, high-k materials need to be researched and developed as gate oxidizing layers. A high-k gate oxidizing layer has lower leakage current compared with the same equivalent oxide thickness and very possibly will replace silicon dioxide to be a gate oxidizing layer of the transistor in the next generation.
The general prior art for the production of a thin high-k metal oxidizing layer chiefly include thermal oxidation, molecular beam epitaxy(MBE), chemical vapor deposition(CVD) and atomic layer deposition (ALD). Therein thermal oxidation requires depositing a layer of metal or a compound containing the metal on the substrate and then producing the metal oxidizing layer by thermal oxidation. Though the traditional method is easy and convenient, the processing must be performed at a high temperature. The metal oxidizing layer can be produced on the substrate directly by MBE, CVD or ALD, instead of expensive installations used to form a high vacuum environment under high temperature.
With regard the technology of 0.13 μm (micron) processing being used in the manufacturing, the thickness of a gate oxidizing layer of a transistor is about equal to 24 Å. When the thickness of a gate oxidizing layer is smaller than 30 Å, isolation of a gate oxidizing layer will be much influenced by the direct tunneling effect, which results in the incremental increase of leakage current of a oxidizing layer to cause power dissipation of the transistor in the closed situation and the possibility of a wrongly switched circuit. When devices are minimized, the current driving ability of the transistors decreases. From the current formula of the metal oxide semiconductor field effect transistor (MOSFET),Id=½·μCOX·W/L (Vgs−Vt)2 wherein,                Id means drain current,        μ means channel mobility,        COX means capacitance of oxidizing layer,        W means channel width,        L means channel length,        Vgs means voltage of gate corresponds to source,        Vt means threshold voltage.        
We know that if we want to increase the current of the transistor, we must first increase COX so as to keep a stable current-driving ability while the characterized size of devices are minimized.
To solve the foregoing problems, it is required to increase physical thickness and value of dielectric constant so as to decrease leakage current of an oxidizing layer and to increase COX. Therefore, using high-k materials to replace silicon dioxide as gate oxidizing layers is a necessary trend. The high-k gate oxidizing layers also calls for high-k gate dielectrics.
It has therefore been tried by the inventor to develop a method of preparing high-k gate dielectrics by liquid phase anodic oxidation, which first produces a metallic film on the surface of clean silicon substrate, next oxidizes said metallic film to form a metallic oxide as a gate oxidizing layer by liquid phase anodic oxidation, and then promotes quality of the gate oxidizing layer by performing a step of thermal annealing. With this oxidation, a gate dielectric layer of high quality, high-k and ultrathin equivalent oxide thickness can be produced, which can be integrated with the complementary metal oxide semiconductor process directly.